Committed to trunk, thanks!
Hi Fei:
> The fix is fine but maybe using s0 instead of t0 is better:
> 1. simpler codes.
> 2. less stack size
>
> current implementaion:
> >+**sd\tt0,40\(sp\)
> >+**frcsr\tt0
> >+**sw\tt0,32\(sp\) //save content of frcsr in stack
>
> use s0:
> >+**sd\tt0,40\(s
On 2023-12-25 16:45 Kito Cheng wrote:
>+++ b/gcc/testsuite/gcc.target/riscv/interrupt-misaligned.c
>@@ -0,0 +1,29 @@
>+/* { dg-do compile } */
>+/* { dg-options "-O2 -march=rv64gc -mabi=lp64d -fno-schedule-insns
>-fno-schedule-insns2" } */
>+/* { dg-skip-if "" { *-*-* } { "-flto -fno-fat-lto-ob
On 12/25/23 01:45, Kito Cheng wrote:
`interrupt` function will backup fcsr register, but it fixed to SImode,
it's not big issue since fcsr only used 8 bits so far, however the
offset should still using UNITS_PER_WORD to prevent the stack offset
become non 8 byte aligned, it will cause problem
`interrupt` function will backup fcsr register, but it fixed to SImode,
it's not big issue since fcsr only used 8 bits so far, however the
offset should still using UNITS_PER_WORD to prevent the stack offset
become non 8 byte aligned, it will cause problem for RV64.
gcc/ChangeLog:
* confi
