: Demin Han ; gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; pan2...@intel.com;
rdapp@gmail.com
Subject: Re: [PATCH] RISC-V: Fix double mode under RV32 not utilize vf
On Fri, Jul 19, 2024 at 12:07 PM Jeff Law
mailto:jeffreya...@gmail.com>> wrote:
On 7/19/24 2
On Fri, Jul 19, 2024 at 11:08 AM Jeff Law wrote:
>
>
>
> On 7/19/24 2:55 AM, demin.han wrote:
> > Currently, some binops of vector vs double scalar under RV32 can't
> > translated to vf but vfmv+vxx.vv.
> >
> > The cause is that vec_duplicate is also expanded to broadcast for double
> > mode
> >
On Fri, Jul 19, 2024 at 12:07 PM Jeff Law wrote:
>
>
> On 7/19/24 2:55 AM, demin.han wrote:
> > Currently, some binops of vector vs double scalar under RV32 can't
> > translated to vf but vfmv+vxx.vv.
> >
> > The cause is that vec_duplicate is also expanded to broadcast for double
> mode
> > unde
On 7/19/24 2:55 AM, demin.han wrote:
Currently, some binops of vector vs double scalar under RV32 can't
translated to vf but vfmv+vxx.vv.
The cause is that vec_duplicate is also expanded to broadcast for double mode
under RV32. last-combine can't process expanded broadcast.
gcc/ChangeLog:
Currently, some binops of vector vs double scalar under RV32 can't
translated to vf but vfmv+vxx.vv.
The cause is that vec_duplicate is also expanded to broadcast for double mode
under RV32. last-combine can't process expanded broadcast.
gcc/ChangeLog:
* config/riscv/vector.md: Add !FLOA
