subject:"\[PATCH\] RISC\-V\: Fix bugs of handling scalar of SEW64 vx instruction in RV32"

RE: [PATCH] RISC-V: Fix bugs of handling scalar of SEW64 vx instruction in RV32

2023-10-30 Thread Li, Pan2

handling scalar of SEW64 vx instruction in RV32 Thanks, LGTM. Regards Robin

Re: [PATCH] RISC-V: Fix bugs of handling scalar of SEW64 vx instruction in RV32

2023-10-30 Thread Robin Dapp

Thanks, LGTM. Regards Robin

[PATCH] RISC-V: Fix bugs of handling scalar of SEW64 vx instruction in RV32

2023-10-27 Thread Juzhe-Zhong

sew64_scalar_helper is handling SEW64 vx instruction pattern on RV32 system. According to RVV ISA, we can directly use vx instruction of SEW64 on RV32 system since RV32 GR reg is 32bit. Consider this following case: vsetvl e64m1 vadd.vx v,v,x will be transform by sew64_scalar_helper: vsetvl e64