> On 11/17/23 07:18, Kito Cheng wrote:
> > I didn’t take a closer look yet on the ira/lra dump yet, but my feeling
> > is that may cause by the earlyclober modifier isn’t work as expect?
> >
> > Let me take closer look tomorrow.
> Remember that constraints aren't checked until register allocation.
On 11/17/23 07:18, Kito Cheng wrote:
I didn’t take a closer look yet on the ira/lra dump yet, but my feeling
is that may cause by the earlyclober modifier isn’t work as expect?
Let me take closer look tomorrow.
Remember that constraints aren't checked until register allocation. So
the comb
; which is wrong.
>
> So. we should emit vsetvl, let GCC known the AVL "a7" used is a different
> value.
> Then bug will be fixed.
>
> But you remind me a thing, is that for whole register mode , we don't need
> this.
> So, the code should be adjusted:
>
e memory address is changed into "a7" which is wrong.
So. we should emit vsetvl, let GCC known the AVL "a7" used is a different value.
Then bug will be fixed.
But you remind me a thing, is that for whole register mode , we don't need this.
So, the code should be adjusted:
> diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
> index 6a2009ffb05..08bbb657a06 100644
> --- a/gcc/config/riscv/riscv-v.cc
> +++ b/gcc/config/riscv/riscv-v.cc
> @@ -374,10 +374,24 @@ void
> emit_vlmax_insn_lra (unsigned icode, unsigned insn_flags, rtx *ops, rtx vl)
> {
>
Fix segment fault on tuple move:
bbl loader
z ra 000102ac sp 003ffaf0 gp 0001c0b8
tp t0 000104a0 t1 000f t2
s0 s1 a0 003ffb30 a1 003ffb58
a2 000
