Re: [PATCH] RISC-V: Fix RVV mask mode size

2023-01-08 Thread Richard Biener via Gcc-patches
On Tue, Dec 27, 2022 at 9:46 PM Jeff Law wrote: > > > > On 12/19/22 00:44, Richard Biener wrote: > > On Sat, Dec 17, 2022 at 2:54 AM Jeff Law via Gcc-patches > > wrote: > >> > >> > >> > >> On 12/16/22 18:44, 钟居哲 wrote: > >>> Yes, VNx4DF only has 4 bit in mask mode in case of load and store. > >>>

Re: [PATCH] RISC-V: Fix RVV mask mode size

2022-12-27 Thread Jeff Law via Gcc-patches
On 12/19/22 00:44, Richard Biener wrote: On Sat, Dec 17, 2022 at 2:54 AM Jeff Law via Gcc-patches wrote: On 12/16/22 18:44, 钟居哲 wrote: Yes, VNx4DF only has 4 bit in mask mode in case of load and store. For example vlm or vsm we will load store 8-bit ??? (I am not sure hardward can load s

Re: [PATCH] RISC-V: Fix RVV mask mode size

2022-12-19 Thread Richard Biener via Gcc-patches
On Sat, Dec 17, 2022 at 2:54 AM Jeff Law via Gcc-patches wrote: > > > > On 12/16/22 18:44, 钟居哲 wrote: > > Yes, VNx4DF only has 4 bit in mask mode in case of load and store. > > For example vlm or vsm we will load store 8-bit ??? (I am not sure > > hardward can load store 4bit,but I am sure it defi

Re: Re: [PATCH] RISC-V: Fix RVV mask mode size

2022-12-16 Thread 钟居哲
.ai From: Jeff Law Date: 2022-12-17 09:53 To: 钟居哲; gcc-patches CC: kito.cheng; palmer Subject: Re: [PATCH] RISC-V: Fix RVV mask mode size On 12/16/22 18:44, 钟居哲 wrote: > Yes, VNx4DF only has 4 bit in mask mode in case of load and store. > For example vlm or vsm we will load store 8-bi

Re: [PATCH] RISC-V: Fix RVV mask mode size

2022-12-16 Thread Jeff Law via Gcc-patches
On 12/16/22 18:44, 钟居哲 wrote: Yes, VNx4DF only has 4 bit in mask mode in case of load and store. For example vlm or vsm we will load store 8-bit ??? (I am not sure hardward can load store 4bit,but I am sure it definetly not load store the whole register size) Most likely than not you end up

Re: Re: [PATCH] RISC-V: Fix RVV mask mode size

2022-12-16 Thread 钟居哲
-patches CC: kito.cheng; palmer Subject: Re: [PATCH] RISC-V: Fix RVV mask mode size On 12/13/22 23:48, juzhe.zh...@rivai.ai wrote: > From: Ju-Zhe Zhong > > This patch is to fix RVV mask modes size. Since mask mode size are adjust > as a whole RVV register size LMUL = 1 which not only ma

Re: [PATCH] RISC-V: Fix RVV mask mode size

2022-12-16 Thread Jeff Law via Gcc-patches
On 12/13/22 23:48, juzhe.zh...@rivai.ai wrote: From: Ju-Zhe Zhong This patch is to fix RVV mask modes size. Since mask mode size are adjust as a whole RVV register size LMUL = 1 which not only make each mask type for example vbool32_t tied to vint8m1_t but also increase memory consuming. I

[PATCH] RISC-V: Fix RVV mask mode size

2022-12-13 Thread juzhe . zhong
From: Ju-Zhe Zhong This patch is to fix RVV mask modes size. Since mask mode size are adjust as a whole RVV register size LMUL = 1 which not only make each mask type for example vbool32_t tied to vint8m1_t but also increase memory consuming. I notice this issue during development of VSETVL PASS.