t; RVV modes supported including QI HI SI DI SF DF excluding HF and BF.
>
>
>
> juzhe.zh...@rivai.ai
>
> From: Jeff Law
> Date: 2022-12-17 09:48
> To: juzhe.zhong; gcc-patches
> CC: kito.cheng; palmer
> Subject: Re: [PATCH] RISC-V: Fix RVV machine mode attribute configu
juzhe.zh...@rivai.ai
From: Jeff Law
Date: 2022-12-17 09:48
To: juzhe.zhong; gcc-patches
CC: kito.cheng; palmer
Subject: Re: [PATCH] RISC-V: Fix RVV machine mode attribute configuration
On 12/14/22 00:01, juzhe.zh...@rivai.ai wrote:
> From: Ju-Zhe Zhong
>
> The attribute configurat
On 12/14/22 00:01, juzhe.zh...@rivai.ai wrote:
From: Ju-Zhe Zhong
The attribute configuration of each machine mode are support in the previous
patch.
I noticed some of them are not correct during VSETVL PASS testsing.
Correct them in the single patch now.
gcc/ChangeLog:
* config/
From: Ju-Zhe Zhong
The attribute configuration of each machine mode are support in the previous
patch.
I noticed some of them are not correct during VSETVL PASS testsing.
Correct them in the single patch now.
gcc/ChangeLog:
* config/riscv/riscv-vector-switch.def (ENTRY): Correct attrib
