hes@gcc.gnu.org
Cc: jeffreya...@gmail.com; juzhe.zh...@rivai.ai; kito.ch...@gmail.com;
jinma.cont...@gmail.com
Subject: Re: [PATCH] RISC-V: Fix ICE for rvv in lto
> I see, I can reproduce this when build "-march=rv64gcv -mabi=lp64d -flto -O0
> test.c -o test.elf".
>
>
> I see, I can reproduce this when build "-march=rv64gcv -mabi=lp64d -flto -O0
> test.c -o test.elf".
>
> #include
>
> int
> main ()
> {
> size_t vl = 8;
> vint32m1_t vs1 = {};
> vint32m1_t vs2 = {};
> vint32m1_t vd = __riscv_vadd_vv_i32m1(vs1, vs2, vl);
>
> return (int)&vd;
> }
>
>
> > I think this is wrong and needs to be fixed, maybe we shouldn't
> > use "ggc_alloc ()", or is there another better
> > way to implement it?
>
> From the root we're marking the registered_functions vector via
> the
>
> template
> void
> gt_ggc_mx (vec *v)
>
> overload which will eventually ma
On Fri, Sep 6, 2024 at 7:31 PM Jin Ma wrote:
>
> When we use flto, the function list of rvv will be generated twice,
> once in the cc1 phase and once in the lto phase. However, due to
> the different generation methods, the two lists are different.
>
> For example, when there is no zvfh or zvfhmin
iginal Message-
From: Jin Ma
Sent: Sunday, September 8, 2024 1:15 PM
To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Cc: jeffreya...@gmail.com; juzhe.zh...@rivai.ai; kito.ch...@gmail.com;
jinma.cont...@gmail.com
Subject: Re: [PATCH] RISC-V: Fix ICE for rvv in lto
> > #include
> >
> &g
> > #include
> >
> > vint32m1_t foo(vint32m1_t vs1, vint32m1_t vs2, size_t vl)
> > {
> > return __riscv_vadd_vv_i32m1(vs1, vs2, vl);
> > }
>
> To double confirm, you mean "riscv64-linux-gnu-gcc-14 -march=rv64gcv
> -mabi=lp64d -flto -O0 tmp.c -c -S -o -" with above is able to reproduce this
On 9/6/24 11:30 AM, Jin Ma wrote:
When we use flto, the function list of rvv will be generated twice,
once in the cc1 phase and once in the lto phase. However, due to
the different generation methods, the two lists are different.
For example, when there is no zvfh or zvfhmin in arch, it is
ge
to reproduce this
ICE?
Pan
-Original Message-
From: Jin Ma
Sent: Saturday, September 7, 2024 5:43 PM
To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Cc: jeffreya...@gmail.com; juzhe.zh...@rivai.ai; kito.ch...@gmail.com;
jinma.cont...@gmail.com
Subject: Re: [PATCH] RISC-V: Fix ICE for rvv in lto
>
> > +/* Test that we do not have ice when compile */
> > +
> > +/* { dg-do run } */
> > +/* { dg-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl -flto
> > -O2 -fno-checking" } */
> > +
> > +#include
> > +
> > +int
> > +main ()
> > +{
> > + size_t vl = 8;
> > + vint32m1_t vs1 = {};
> >
that should be covered by test already.
Pan
-Original Message-
From: Jin Ma
Sent: Saturday, September 7, 2024 1:31 AM
To: gcc-patches@gcc.gnu.org
Cc: jeffreya...@gmail.com; juzhe.zh...@rivai.ai; Li, Pan2 ;
kito.ch...@gmail.com; jinma.cont...@gmail.com; Jin Ma
Subject: [PATCH] RISC-V:
When we use flto, the function list of rvv will be generated twice,
once in the cc1 phase and once in the lto phase. However, due to
the different generation methods, the two lists are different.
For example, when there is no zvfh or zvfhmin in arch, it is
generated by calling function "riscv_prag
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