Re: [PATCH] RISC-V: Expand subreg move via slide if necessary [PR116086].

> > Like aarch64 we set REGMODE_NATURAL_SIZE for fixed-size modes to > > UNITS_PER_WORD. Isn't that part of the problem? > > > > In extract_bit_field_as_subreg we check lowpart_bit_field_p (= true because > > 128 is a multiple of UNITS_PER_WORD). This leads to the subreg expression. > > > > If I

Re: [PATCH] RISC-V: Expand subreg move via slide if necessary [PR116086].

"Robin Dapp" writes: >> > IMO, what ought to happen here is that the RA should spill >> > the inner register to memory and load the V4SI back from there. >> > (Or vice versa, for an lvalue.) Obviously that's not very efficient, >> > and so a patch like the above might be useful as an optimisation

Re: [PATCH] RISC-V: Expand subreg move via slide if necessary [PR116086].

> > IMO, what ought to happen here is that the RA should spill > > the inner register to memory and load the V4SI back from there. > > (Or vice versa, for an lvalue.) Obviously that's not very efficient, > > and so a patch like the above might be useful as an optimisation.[*] > > But it shouldn't

Re: [PATCH] RISC-V: Expand subreg move via slide if necessary [PR116086].

Richard Sandiford writes: > A somewhat similar situation can happen for SVE with subregs like: > > (subreg:V4SI (reg:VNx8SI R) 16) > > IMO, what ought to happen here is that the RA should spill > the inner register to memory and load the V4SI back from there. > (Or vice versa, for an lvalue.) O

Re: [PATCH] RISC-V: Expand subreg move via slide if necessary [PR116086].

Jeff Law writes: > On 7/26/24 2:42 PM, Robin Dapp wrote: >> Hi, >> >> when the source mode is potentially larger than one vector (e.g. an >> LMUL2 mode for VLEN=128) we don't know which vector the subreg actually >> refers to. For zvl128b and LMUL=2 the subreg in (subreg:V2DI (reg:V4DI)) >> coul

Re: [PATCH] RISC-V: Expand subreg move via slide if necessary [PR116086].

On 7/26/24 2:42 PM, Robin Dapp wrote: Hi, when the source mode is potentially larger than one vector (e.g. an LMUL2 mode for VLEN=128) we don't know which vector the subreg actually refers to. For zvl128b and LMUL=2 the subreg in (subreg:V2DI (reg:V4DI)) could actually be the a full (high) v

[PATCH] RISC-V: Expand subreg move via slide if necessary [PR116086].

Hi, when the source mode is potentially larger than one vector (e.g. an LMUL2 mode for VLEN=128) we don't know which vector the subreg actually refers to. For zvl128b and LMUL=2 the subreg in (subreg:V2DI (reg:V4DI)) could actually be the a full (high) vector register of a two-register group (at