Re:RE: [PATCH] RISC-V: Ensure vector args and return use function stack to pass [PR110119]

2023-06-14 Thread Lehua Ding
> Nit for test. > +/* { dg-options "-march=rv64gczve32x > +--param=riscv-autovec-preference=fixed-vlmax" } */ > To > +/* { dg-options "-march=rv64gc_zve32x --param=riscv-autovec-preference=fixed-vlmax" } */ Fixed in the V2 patch (https://gcc.gnu.org/pipermail/gcc-patches/2023-June/621698.html), t

RE: Re: [PATCH] RISC-V: Ensure vector args and return use function stack to pass [PR110119]

2023-06-14 Thread Li, Pan2 via Gcc-patches
.zh...@rivai.ai Sent: Wednesday, June 14, 2023 7:21 PM To: 丁乐华 ; gcc-patches Cc: jeffreyalaw ; Robin Dapp ; palmer Subject: 回复: Re: [PATCH] RISC-V: Ensure vector args and return use function stack to pass [PR110119] Also p110119-1.c change name of test into pr110119-1.c juzhe.zh...@riva

Re: [PATCH] RISC-V: Ensure vector args and return use function stack to pass [PR110119]

2023-06-14 Thread Lehua Ding
> \ No newline at end of file > Add newline for each test. Address this comment, below is the V2 patch link. https://gcc.gnu.org/pipermail/gcc-patches/2023-June/621698.html   Best, Lehua  

Re: [PATCH] RISC-V: Ensure vector args and return use function stack to pass [PR110119]

2023-06-14 Thread Lehua Ding
> so this is intended to fix the PR as well as unblock while we continue > with the preliminary ABI separately? Yes, and I will send the new prerelease vector calling convention later. Best, Lehua

Re: [PATCH] RISC-V: Ensure vector args and return use function stack to pass [PR110119]

2023-06-14 Thread Robin Dapp via Gcc-patches
Hi, > Thanks for fixing this. > > This patch let RVV type (both vector and tuple) return in memory by > default when there is no vector ABI support. It makes sens to me. > > CC more RISC-V folks to comments. so this is intended to fix the PR as well as unblock while we continue with the prelimi

Re: Re: [PATCH] RISC-V: Ensure vector args and return use function stack to pass [PR110119]

2023-06-14 Thread juzhe.zh...@rivai.ai
\ No newline at end of file Add newline for each test. juzhe.zh...@rivai.ai From: Lehua Ding Date: 2023-06-14 19:33 To: 钟居哲; gcc-patches CC: Jeff Law; Robin Dapp; palmer Subject: Re: [PATCH] RISC-V: Ensure vector args and return use function stack to pass [PR110119] Fix all comment from

Re: [PATCH] RISC-V: Ensure vector args and return use function stack to pass [PR110119]

2023-06-14 Thread Lehua Ding
Fix all comment from Juzhe, thanks. Below is the new patch. Please use the attachment if there is a problem with the format of the patch below. PR 110119 gcc/ChangeLog: * config/riscv/riscv.cc (riscv_get_arg_info): Return NULL_RTX for vector mode (riscv_pass_by_refer

回复: Re: [PATCH] RISC-V: Ensure vector args and return use function stack to pass [PR110119]

2023-06-14 Thread juzhe.zh...@rivai.ai
Also p110119-1.c change name of test into pr110119-1.c juzhe.zh...@rivai.ai 发件人: juzhe.zh...@rivai.ai 发送时间: 2023-06-14 19:17 收件人: 丁乐华; gcc-patches 抄送: jeffreyalaw; Robin Dapp; palmer 主题: Re: [PATCH] RISC-V: Ensure vector args and return use function stack to pass [PR110119] Oh. I see. Change

Re: [PATCH] RISC-V: Ensure vector args and return use function stack to pass [PR110119]

2023-06-14 Thread juzhe.zh...@rivai.ai
riscv_v_ext_tuple_mode_p juzhe.zh...@rivai.ai From: Lehua Ding Date: 2023-06-14 19:03 To: gcc-patches; juzhe.zhong Subject: [PATCH] RISC-V: Ensure vector args and return use function stack to pass [PR110119] Hi, The reason for this bug is that in the case where the vector register is set to a fixed length (with

Re: [PATCH] RISC-V: Ensure vector args and return use function stack to pass [PR110119]

2023-06-14 Thread juzhe.zh...@rivai.ai
Subject: [PATCH] RISC-V: Ensure vector args and return use function stack to pass [PR110119] Hi, The reason for this bug is that in the case where the vector register is set to a fixed length (with `--param=riscv-autovec-preference=fixed-vlmax` option), TARGET_PASS_BY_REFERENCE thinks that

[PATCH] RISC-V: Ensure vector args and return use function stack to pass [PR110119]

2023-06-14 Thread Lehua Ding
Hi, The reason for this bug is that in the case where the vector register is set to a fixed length (with `--param=riscv-autovec-preference=fixed-vlmax` option), TARGET_PASS_BY_REFERENCE thinks that variables of type vint32m1 can be passed through two scalar registers, but when GCC calls FUNCTION_V