I agree with Kito; I don't support merging this patch. My reasoning is twofold:
- The default settings should be fairly neutral, avoiding codegen that
severely disadvantages some targets. Misaligned memory accesses are
certainly a problematic case in that respect. (And it's highly
asymmetric: t
-1 for this, default enable fast unaligned access could cause many
problems, and lots of RISC-V cores
don't support HW unaligned access (Rocket-base RISC-V core, most
SiFive core, and most Andes core IIRC),
change this to default means package from RISC-V linux distro might
contain unaligned access
On Tue, Oct 4, 2022 at 8:55 PM Palmer Dabbelt wrote:
>
> The C906 is by far the most widely available RISC-V processor, so let's
> default to tuning for it.
>
> gcc/ChangeLog
>
> * config/riscv/riscv.h (RISCV_TUNE_STRING_DEFAULT): Change to
> thead-c906.
> * doc/invoke.texi
The C906 is by far the most widely available RISC-V processor, so let's
default to tuning for it.
gcc/ChangeLog
* config/riscv/riscv.h (RISCV_TUNE_STRING_DEFAULT): Change to
thead-c906.
* doc/invoke.texi (RISC-V -mtune): Change the default to
thead-c906.
---
This
