Re: [PATCH] RISC-V: Allow zero operand for DI variants of vssubu.vx

On 9/18/24 1:41 AM, Kito Cheng wrote: LGTM, thanks :) Agreed and pushed. Bohan Lei > 於 2024年9月18日 週三 05:28 寫道： The RISC-V vector machine description relies on the helper function `sew64_scalar_helper` to emit actual insns for the DI variants of

Re: [PATCH] RISC-V: Allow zero operand for DI variants of vssubu.vx

LGTM, thanks :) Bohan Lei 於 2024年9月18日 週三 05:28 寫道： > The RISC-V vector machine description relies on the helper function > `sew64_scalar_helper` to emit actual insns for the DI variants of > vssub.vx and vssubu.vx. This works with vssub.vx, but can cause > problems with vssubu.vx with the scal

[PATCH] RISC-V: Allow zero operand for DI variants of vssubu.vx

The RISC-V vector machine description relies on the helper function `sew64_scalar_helper` to emit actual insns for the DI variants of vssub.vx and vssubu.vx. This works with vssub.vx, but can cause problems with vssubu.vx with the scalar operand being constant zero, because `has_vi_variant_p` retu