Re: [PATCH] RISC-V: Align vconfig for TARGER_SFB_ALU

2024-09-19 Thread Robin Dapp
Hi Dusan, sorry for the late reply. > This patch addresses a missed opportunity to fuse vsetvl_infos. > Instead of checking whether demands for merging configurations of > vsetvl_info are all met, the demands are checked individually. > > The case in question occurs because of the conditional

[PATCH] RISC-V: Align vconfig for TARGER_SFB_ALU

2024-09-10 Thread Dusan Stojkovic
This patch addresses a missed opportunity to fuse vsetvl_infos. Instead of checking whether demands for merging configurations of vsetvl_info are all met, the demands are checked individually. The case in question occurs because of the conditional move instruction which sifive-7, sifive-p400 a