Re: [PATCH] RISC-V: Add tt-ascalon-d8 pipeline description

2025-09-02 Thread Jeff Law
On 9/2/25 6:17 AM, Anton Blanchard wrote: Did you run Kito's pipeline checker script? I suspect it'll tell you you need a few more cases in your model. Essentially we have checking asserts that require every insn to have a mapping to a reservation. So someone could ask for code gen for

Re: [PATCH] RISC-V: Add tt-ascalon-d8 pipeline description

2025-09-02 Thread Anton Blanchard
Hi Jeff, > > I modelled decode since the aggregate issue bandwidth (for the right > > sequence > > of instructions) is way above this. Not sure if it's necessary but it felt > > like > > the right thing to do. > There's no 100% right answer every time on this kind of stuff. If it > seems to be

Re: [PATCH] RISC-V: Add tt-ascalon-d8 pipeline description

2025-08-23 Thread Jeff Law
On 8/21/25 11:48 PM, Anton Blanchard wrote: Add pipeline description for the Tenstorrent Ascalon 8 wide CPU. gcc/ChangeLog: * config/riscv/riscv-cores.def (RISCV_TUNE): Update. * config/riscv/riscv-opts.h (enum riscv_microarchitecture_type): Add tt_ascalon_d8.

[PATCH] RISC-V: Add tt-ascalon-d8 pipeline description

2025-08-21 Thread Anton Blanchard
Add pipeline description for the Tenstorrent Ascalon 8 wide CPU. gcc/ChangeLog: * config/riscv/riscv-cores.def (RISCV_TUNE): Update. * config/riscv/riscv-opts.h (enum riscv_microarchitecture_type): Add tt_ascalon_d8. * config/riscv/riscv.md: Update tune attribute