Subject: [PATCH] RISC-V: Add testcases for unsigned vector SAT_SUB form 11 and
form 12
From: panciyan
This patch adds testcase for form11 and form12, as shown below:
void __attribute__((noinline)) \
vec_sat_u_sub_##T##_fmt_11 (T *out, T *op_1, T *op_2
From: panciyan
This patch adds testcase for form11 and form12, as shown below:
void __attribute__((noinline)) \
vec_sat_u_sub_##T##_fmt_11 (T *out, T *op_1, T *op_2, unsigned limit) \
{\
u
day, July 10, 2025 3:14 PM
To: gcc-patches@gcc.gnu.org
Cc: kito.ch...@gmail.com; richard.guent...@gmail.com; tamar.christ...@arm.com;
juzhe.zh...@rivai.ai; Li, Pan2 ; jeffreya...@gmail.com;
rdapp@gmail.com; panciyan
Subject: [PATCH] RISC-V: Add testcases for unsigned vector SAT_SUB form 11
From: panciyan
This patch adds testcase for form11 and form12, as shown below:
void __attribute__((noinline)) \
vec_sat_u_sub_##T##_fmt_11 (T *out, T *op_1, T *op_2, unsigned limit) \
{\
u
juzhe.zh...@rivai.ai; Li, Pan2 ; jeffreya...@gmail.com;
rdapp@gmail.com; panciyan
Subject: [PATCH] RISC-V: Add testcases for unsigned vector SAT_SUB form 11 and
form 12
From: panciyan
This patch adds testcase for form11 and form12, as shown below:
void __a
From: panciyan
This patch adds testcase for form11 and form12, as shown below:
void __attribute__((noinline)) \
vec_sat_u_sub_##T##_fmt_11 (T *out, T *op_1, T *op_2, unsigned limit) \
{\
u