Re: [PATCH] RISC-V: Add testcases for unsigned imm vec SAT_SUB form1

LGTM juzhe.zh...@rivai.ai From: Li Xu Date: 2024-11-08 14:57 To: gcc-patches CC: kito.cheng; palmer; juzhe.zhong; xuli Subject: [PATCH] RISC-V: Add testcases for unsigned imm vec SAT_SUB form1 From: xuli form1: void __attribute__((noinline)) \ vec_sat_u_sub_imm##IMM##_##T

[PATCH] RISC-V: Add testcases for unsigned imm vec SAT_SUB form1

From: xuli form1: void __attribute__((noinline)) \ vec_sat_u_sub_imm##IMM##_##T##_fmt_1 (T *out, T *in, unsigned limit) \ { \ unsigned i; \ for (i = 0; i < limit; i++) \