Hi Jeff, Robin,
Thanks for your comments.
On 30/03/2025 01:30, Jeff Law wrote:
On 3/27/25 1:39 PM, Robin Dapp wrote:
Hi Paul-Antoine,
This pattern enables the combine pass to merge a vec_duplicate into a
plus-mult
or minus-mult RTL instruction.
Before this patch, we have two instructions,
So may be the way to go is add a field to the uarch tuning structure
indicating the additional cost (if any) of a register file crossing vector op
of this nature. Then query that in riscv_rtx_costs or whatever our rtx_cost
function is named.
Default that additional cost to zero initially. Th
in and Jeff, I will re-send the patch of vadd.vv/vx after stage
1 open, and then all other
similar cases.
Pan
-Original Message-
From: Jeff Law
Sent: Sunday, March 30, 2025 8:31 AM
To: Robin Dapp ; Paul-Antoine Arras ;
gcc-patches@gcc.gnu.org; Li, Pan2
Subject: Re: [PATCH] RISC-V:
On 3/27/25 1:39 PM, Robin Dapp wrote:
Hi Paul-Antoine,
This pattern enables the combine pass to merge a vec_duplicate into a
plus-mult
or minus-mult RTL instruction.
Before this patch, we have two instructions, e.g.:
vfmv.v.f v6,fa0
vfmadd.vv v9,v6,v7
After, we get only o
Hi Paul-Antoine,
This pattern enables the combine pass to merge a vec_duplicate into a plus-mult
or minus-mult RTL instruction.
Before this patch, we have two instructions, e.g.:
vfmv.v.fv6,fa0
vfmadd.vv v9,v6,v7
After, we get only one:
vfmadd.vf v9,fa0,v7
On SPEC201
This pattern enables the combine pass to merge a vec_duplicate into a plus-mult
or minus-mult RTL instruction.
Before this patch, we have two instructions, e.g.:
vfmv.v.fv6,fa0
vfmadd.vv v9,v6,v7
After, we get only one:
vfmadd.vf v9,fa0,v7
On SPEC2017's 503.bwaves_r, de
