Re: [PATCH] RISC-V: Add autovec mode param.

Could you make a simple testcase that could vectorize two loops in different modes (e.g one SI and one SF) and with this param will only auto vec on loop? I added a test now in the attached v2 that checks that we vectorize with the requested mode. Right now the patch only takes away "additiona

Re: [PATCH] RISC-V: Add autovec mode param.

Could you make a simple testcase that could vectorize two loops in different modes (e.g one SI and one SF) and with this param will only auto vec on loop? On Wed, May 21, 2025 at 9:47 PM Robin Dapp wrote: > > Hi, > > This patch adds a --param=autovec-mode=. When the param is > specified we make

[PATCH] RISC-V: Add autovec mode param.

Hi, This patch adds a --param=autovec-mode=. When the param is specified we make autovectorize_vector_modes return exactly this mode if it is available. This helps when testing different vectorizer settings. Regtested on rv64gcv_zvl512b. Regards Robin gcc/ChangeLog: * config/riscv/r