> -原始邮件-
> 发件人: "Jeff Law"
> 发送时间: 2022-11-21 23:26:37 (星期一)
> 收件人: "juzhe.zh...@rivai.ai" , schwab
> 抄送: gcc-patches , "monk.chiang"
, "kito.cheng" , jiawei
> 主题: Re: [PATCH] RISC-V: Add RVV registers register spil
On 11/21/22 02:25, juzhe.zh...@rivai.ai wrote:
https://gcc.gnu.org/pipermail/gcc-patches/2022-November/606523.html
This patch obviously didn't include scalable size frame.
So it ICE in offset = cfun->machine->frame.gp_sp_offset.to_constant ();
We can't directly use to_constant if the frame is a
evert it. Thanks
juzhe.zh...@rivai.ai
From: juzhe.zh...@rivai.ai
Date: 2022-11-21 16:38
To: schwab
CC: gcc-patches; monk.chiang; kito.cheng; jiawei
Subject: Re: Re: [PATCH] RISC-V: Add RVV registers register spilling
This ICE is introduced by this patch:
https://gcc.gnu.org/pipermail/gcc-patch
-V: Add RVV registers register spilling
FAIL: gcc.target/riscv/rvv/base/spill-1.c (internal compiler error: in
to_constant, at poly-int.h:504)
FAIL: gcc.target/riscv/rvv/base/spill-1.c (test for excess errors)
FAIL: gcc.target/riscv/rvv/base/spill-2.c (internal compiler error: in
to_constant, at
FAIL: gcc.target/riscv/rvv/base/spill-1.c (internal compiler error: in
to_constant, at poly-int.h:504)
FAIL: gcc.target/riscv/rvv/base/spill-1.c (test for excess errors)
FAIL: gcc.target/riscv/rvv/base/spill-2.c (internal compiler error: in
to_constant, at poly-int.h:504)
FAIL: gcc.target/riscv/r
Committed, thanks !
On Sun, Nov 6, 2022 at 1:57 AM wrote:
>
> From: Ju-Zhe Zhong
>
> This patch support RVV scalable register spilling.
> prologue && epilogue handling pick up prototype from Monk Chiang
> .
> Co-authored-by: Monk Chiang
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-v.cc
From: Ju-Zhe Zhong
This patch support RVV scalable register spilling.
prologue && epilogue handling pick up prototype from Monk Chiang
.
Co-authored-by: Monk Chiang
gcc/ChangeLog:
* config/riscv/riscv-v.cc (emit_pred_move): Adjust for scalable
register spilling.
(legitimize_m
