Re: [PATCH] RISC-V: Add 'bclr+binv' peephole2 optimization.

2025-06-11 Thread Jiawei
在 2025/6/10 7:20, Jeff Law 写道: On 6/5/25 6:25 AM, Jiawei wrote: Thanks for your suggestions, I found that the ior is successful generated in combine pass without using the zbs extension, and in other architecture it also work fine. Yea, it's probably an artifact of how we need to represe

Re: [PATCH] RISC-V: Add 'bclr+binv' peephole2 optimization.

2025-06-09 Thread Jeff Law
On 6/5/25 6:25 AM, Jiawei wrote: Thanks for your suggestions, I found that the ior is successful generated in combine pass without using the zbs extension, and in other architecture it also work fine. Yea, it's probably an artifact of how we need to represent the single bit clear. It's r

Re: [PATCH] RISC-V: Add 'bclr+binv' peephole2 optimization.

2025-06-05 Thread Jiawei
在 2025/5/30 1:46, Jeff Law 写道: On 5/28/25 9:05 PM, Jiawei wrote: This seems like it would be much better as a combine pattern.   In fact, I'm a bit surprised that combine didn't simplify this series of operations into a IOR. So I'd really like to see the .combine dump with and without thi

Re: [PATCH] RISC-V: Add 'bclr+binv' peephole2 optimization.

2025-05-29 Thread Jeff Law
On 5/28/25 9:05 PM, Jiawei wrote: This seems like it would be much better as a combine pattern.   In fact, I'm a bit surprised that combine didn't simplify this series of operations into a IOR.  So I'd really like to see the .combine dump with and without this hunk for the relevant testcas

Re: [PATCH] RISC-V: Add 'bclr+binv' peephole2 optimization.

2025-05-28 Thread Jiawei
在 2025/5/29 0:13, Jeff Law 写道: On 5/28/25 4:23 AM, Jiawei wrote: This patch adds a peephole2 optimization that combines a 'bclr' followed by a 'binv' into a single 'bset' instruction when the Zbs extension is enabled. The motivation for this patch is that PR116398 limits 2→2 RTL combinat

Re: [PATCH] RISC-V: Add 'bclr+binv' peephole2 optimization.

2025-05-28 Thread Jeff Law
On 5/28/25 4:23 AM, Jiawei wrote: This patch adds a peephole2 optimization that combines a 'bclr' followed by a 'binv' into a single 'bset' instruction when the Zbs extension is enabled. The motivation for this patch is that PR116398 limits 2→2 RTL combinations, which prevents certain simplif

[PATCH] RISC-V: Add 'bclr+binv' peephole2 optimization.

2025-05-28 Thread Jiawei
This patch adds a peephole2 optimization that combines a 'bclr' followed by a 'binv' into a single 'bset' instruction when the Zbs extension is enabled. The motivation for this patch is that PR116398 limits 2→2 RTL combinations, which prevents certain simplifications in the combiner pass. As a res