On Tue, Aug 04, 2020 at 10:40:15PM -0400, Michael Meissner wrote:
> The power10 processor adds 3 new instructions (BRH, BRW, BRD) that byte swaps
> half-words, words, and double-words within a GPR register.
The brh insn reverses the bytes in each of four 16-bit words in a GPR,
but this patch only
Power10: Add BRH, BRW, BRD support.
The power10 processor adds 3 new instructions (BRH, BRW, BRD) that byte swaps
half-words, words, and double-words within a GPR register. This patch adds
support for these instructions. I have applied the suggestions from the
previous times I have submitted thi
