On Mon, Feb 06, 2017 at 01:28:29PM -0500, Michael Meissner wrote:
> Can I check it into the trunk?
Yes please. Thanks,
Segher
> 2017-02-06 Michael Meissner
>
> PR target/66144
> * config/rs6000/vector.md (vcond): Allow the true and
> false values to be constant vectors wi
On Fri, Feb 03, 2017 at 06:07:56PM -0600, Segher Boessenkool wrote:
> On Fri, Feb 03, 2017 at 04:25:00PM -0500, Michael Meissner wrote:
> > +;; Return 1 if operand is either a vector constant of all 0 bits of a
> > vector
> > +;; constant of all 1 bits.
> > +(define_predicate "vector_int_same_bit"
On Fri, Feb 03, 2017 at 06:07:56PM -0600, Segher Boessenkool wrote:
> On Fri, Feb 03, 2017 at 04:25:00PM -0500, Michael Meissner wrote:
> > +;; Return 1 if operand is either a vector constant of all 0 bits of a
> > vector
> > +;; constant of all 1 bits.
> > +(define_predicate "vector_int_same_bit"
On Fri, Feb 03, 2017 at 04:25:00PM -0500, Michael Meissner wrote:
> +;; Return 1 if operand is either a vector constant of all 0 bits of a vector
> +;; constant of all 1 bits.
> +(define_predicate "vector_int_same_bit"
> + (match_code "const_vector")
> +{
> + if (GET_MODE_CLASS (mode) != MODE_VEC
This patch improves the code generation for:
vector char
compare_vc (vector char a, vector char b)
{
return a == b;
}
Previously it generated:
vcmpequb 2,2,3
vspltisw 1,-1
vspltisw 0,0
xxsel 34,32,33,34
and now it generat
