gt; +FUNC_ATOMIC (int64_t, nand)
> > +FUNC_ATOMIC (int64_t, or)
> > +FUNC_ATOMIC (int64_t, xor)
> > +FUNC_ATOMIC (int, and)
> > +FUNC_ATOMIC (int, nand)
> > +FUNC_ATOMIC (int, or)
> > +FUNC_ATOMIC (int, xor)
> > +FUNC_ATOMIC (short, and)
> > +FUNC_
On Sat, Nov 13, 2021 at 3:34 AM Hongyu Wang wrote:
>
> Hi,
>
> From the CPU's point of view, getting a cache line for writing is more
> expensive than reading. See Appendix A.2 Spinlock in:
>
> https://www.intel.com/content/dam/www/public/us/en/documents/white-papers/
> xeon-lock-scaling-analysis
Hi,
>From the CPU's point of view, getting a cache line for writing is more
expensive than reading. See Appendix A.2 Spinlock in:
https://www.intel.com/content/dam/www/public/us/en/documents/white-papers/
xeon-lock-scaling-analysis-paper.pdf
The full compare and swap will grab the cache line ex
