On Wed, 26 Jan 2022, YunQiang Su wrote:
> Since MIPS r2, the IPL section in Cause register has been expand
> to 8bit instead of 6bit.
Hmm, I cannot see it in my copy of the architecture manual I'm afraid.
The interpretation may have changed, but the field is still 6-bit (not
counting the soft
Since MIPS r2, the IPL section in Cause register has been expand
to 8bit instead of 6bit.
Since __attribute__((interrupt)) is only supported for r2+,
we don't need to detect the target.
gcc/ChangeLog:
* config/mips/mips.cc (mips_expand_prologue):
IPL is 8bit for r2+.
---
gcc/c
