On Sat, 16 Nov 2013, Richard Sandiford wrote:
> So the reasoning is that, after your RECIP.fmt patch, the only direct uses
> of ISA_HAS_FP4 for instruction selection are indexed loads and stores.
> That's why extending them to ISA_MIPS32R2 && !TARGET_FLOAT64 allows
> ISA_HAS_FP4 to be simplified.
"Maciej W. Rozycki" writes:
> 2013-11-14 Maciej W. Rozycki
>
> gcc/
> * config/mips/mips.h (ISA_HAS_FP4): Remove TARGET_FLOAT64
> restriction for ISA_MIPS32R2.
> (ISA_HAS_FP_MADD4_MSUB4): Remove ISA_MIPS32R2 special-casing.
> (ISA_HAS_NMADD4_NMSUB4): Likewise.
>
Hi,
Complementing the recent change to enable FP MADD instructions on
MIPS32r2 processors in the 32-bit FPR mode (CP0.Status.FR=0) here's one to
enable FP ordinary indexed memory access (i.e. LWXC1, SWXC1, LDXC1 and
SDXC1) instructions in that case as well. Architecture documents have
been a
