Andrew Bennett writes:
>> -Original Message-
>> From: Richard Sandiford [mailto:rdsandif...@googlemail.com]
>> Sent: 09 May 2014 12:07
>> To: Andrew Bennett
>> Cc: gcc-patches@gcc.gnu.org; Matthew Fortune; Saeed Ghazanfar; Rich Fuhler
>> Subject: Re: [P
> -Original Message-
> From: Richard Sandiford [mailto:rdsandif...@googlemail.com]
> Sent: 09 May 2014 12:07
> To: Andrew Bennett
> Cc: gcc-patches@gcc.gnu.org; Matthew Fortune; Saeed Ghazanfar; Rich Fuhler
> Subject: Re: [PATCH] Add support for MIPS r3 and r5
>
>
Andrew Bennett writes:
>> > @@ -141,7 +151,8 @@ along with GCC; see the file COPYING3. If not see
>> >"%{EL:-m elf32lmip} \
>> > %{EB:-m elf32bmip} \
>> > %(endian_spec) \
>> > - %{G*} %{mips1} %{mips2} %{mips3} %{mips4} %{mips32} %{mips32r2}
>> %{mips64} \
>> > + %{G*} %{mips1} %
> -Original Message-
> From: Richard Sandiford [mailto:rdsandif...@googlemail.com]
> Sent: 08 May 2014 20:28
> To: Andrew Bennett
> Cc: gcc-patches@gcc.gnu.org; Matthew Fortune; Saeed Ghazanfar; Rich Fuhler
> Subject: Re: [PATCH] Add support for MIPS r3 and r5
>
>
Andrew Bennett writes:
> diff --git a/gcc/config/mips/mips-cpus.def b/gcc/config/mips/mips-cpus.def
> index 07fbf9c..f2e23c6 100644
> --- a/gcc/config/mips/mips-cpus.def
> +++ b/gcc/config/mips/mips-cpus.def
> @@ -44,9 +44,13 @@ MIPS_CPU ("mips4", PROCESSOR_R8000, 4, 0)
> isn't tuned to a spec
On Thu, 8 May 2014, Andrew Bennett wrote:
> Hi,
>
> This patch adds support for MIPS r3 and r5 to GCC. I have updated the msgid
> strings in the .po files for the error message I changed. Can I assume the
> actual msgstr entries will be updated later on?
Never modify .po files in GCC; they sh
