Re: [PATCH] Aarch64: Prevent use of SIMD fcvtz[su] instruction variant with "nosimd"

mihailo.stojano...@typhoon-hil.com writes: > From: Mihailo Stojanovic > > Hi all, > > Currently, SF->SI and DF->DI conversions on Aarch64 with the "nosimd" > flag provided sometimes cause the emitting of a vector variant of the > fcvtz[su] instruction (e.g. fcvtzu s0, s0). > > This modifies the co

[PING][PATCH] Aarch64: Prevent use of SIMD fcvtz[su] instruction variant with "nosimd"

From: Mihailo Stojanovic Hi all, Currently, SF->SI and DF->DI conversions on Aarch64 with the "nosimd" flag provided sometimes cause the emitting of a vector variant of the fcvtz[su] instruction (e.g. fcvtzu s0, s0). This modifies the corresponding pattern to only select the vector variant of t

[PATCH] Aarch64: Prevent use of SIMD fcvtz[su] instruction variant with "nosimd"

From: Mihailo Stojanovic Hi all, Currently, SF->SI and DF->DI conversions on Aarch64 with the "nosimd" flag provided sometimes cause the emitting of a vector variant of the fcvtz[su] instruction (e.g. fcvtzu s0, s0). This modifies the corresponding pattern to only select the vector variant of t