Thanks for the patch and sorry for the slow review.
Eikansh Gupta writes:
> Many of the constants which are generated using 3 `mov` instruction can be
> generated using `mov` plus `sub` instruction. The patch uses following method
> to add the mentioned functionality. If a constant `val` can not
Many of the constants which are generated using 3 `mov` instruction can be
generated using `mov` plus `sub` instruction. The patch uses following method
to add the mentioned functionality. If a constant `val` can not be generated
using 1 or 2 `mov`, then find `val1` such that `(val + val1)` can be
On 19/10/2023 13:43, Wilco Dijkstra wrote:
Further improve immediate generation by adding support for 2-instruction
MOV/EOR bitmask immediates. This reduces the number of 3/4-instruction
immediates in SPECCPU2017 by ~2%.
Passes regress, OK for commit?
gcc/ChangeLog:
* config/aarch64
Further improve immediate generation by adding support for 2-instruction
MOV/EOR bitmask immediates. This reduces the number of 3/4-instruction
immediates in SPECCPU2017 by ~2%.
Passes regress, OK for commit?
gcc/ChangeLog:
* config/aarch64/aarch64.cc (aarch64_internal_mov_immediate)