On Fri, Jun 04, 2021 at 01:03:58AM +, Liu, Hongtao wrote:
> Thanks for the review.
> Yes, you're right, AVX512VL parts are already guaranteed by
> ix86_hard_regno_mode_ok.
>
> Here is updated patch.
One remaining thing, could you try to modify the testcase back to
#include and using intrins
>-Original Message-
>From: Jakub Jelinek
>Sent: Thursday, June 3, 2021 9:49 PM
>To: Liu, Hongtao
>Cc: gcc-patches@gcc.gnu.org
>Subject: Re: [PATCH] [i386] Fix ICE of insn does not satisfy its constraints.
>
>On Thu, Jun 03, 2021 at 05:07:26PM +0800, liuhon
On Thu, Jun 03, 2021 at 05:07:26PM +0800, liuhongt via Gcc-patches wrote:
> @@ -18163,10 +18163,10 @@ (define_expand "v16qiv16si2"
>"TARGET_AVX512F")
>
> (define_insn "avx2_v8qiv8si2"
> - [(set (match_operand:V8SI 0 "register_operand" "=v")
> + [(set (match_operand:V8SI 0 "register_operand
For evex encoding extended instructions, when vector length is less
than 512 bits, AVX512VL is needed, besides some instructions like
vpmovzxbx need extra AVX512BW. So this patch refines corresponding
constraints, i.e. from "v/vm" to "Yv/Yvm", from "v/vm" to "Yw/Ywm".
Bootstrapped and regtested on
