Hi Alex,
> -Original Message-
> From: Alex Coplan
> Sent: 26 June 2020 10:38
> To: Alex Coplan ; Kyrylo Tkachov
> ; gcc-patches@gcc.gnu.org
> Cc: Richard Earnshaw ; nd ;
> Ramana Radhakrishnan
> Subject: RE: [PATCH] [arm] Don't generate invalid LDRD insns
> -Original Message-
> From: Gcc-patches On Behalf Of Alex
> Coplan
> Sent: 18 May 2020 16:37
> To: Kyrylo Tkachov ; gcc-patches@gcc.gnu.org
> Cc: Richard Earnshaw ; nd ; Ramana
> Radhakrishnan
> Subject: RE: [PATCH] [arm] Don't generate invalid LDRD insns
> -Original Message-
> From: Kyrylo Tkachov
> Sent: 15 May 2020 11:57
> To: Alex Coplan ; gcc-patches@gcc.gnu.org
> Cc: nd ; ni...@redhat.com; Richard Earnshaw
> ; Ramana Radhakrishnan
>
> Subject: RE: [PATCH] [arm] Don't generate invalid LDRD insns
>
Hi Alex,
> -Original Message-
> From: Alex Coplan
> Sent: 15 May 2020 11:36
> To: gcc-patches@gcc.gnu.org
> Cc: nd ; ni...@redhat.com; Richard Earnshaw
> ; Ramana Radhakrishnan
> ; Kyrylo Tkachov
>
> Subject: [PATCH] [arm] Don't generate invalid LDRD i
Hello,
This patch fixes a bug in the arm backend where GCC generates invalid LDRD
instructions. The LDRD instruction requires the first transfer register to be
even, but GCC attempts to use odd registers here. For example, with the
following C code:
struct c {
double a;
} __attribut
