Re: [PATCH] [aarch64] Correct the maximum shift amount for shifted operands.

> On 08.11.2018, at 13:25, Kyrill Tkachov wrote: > > Hi Christoph, > > On 08/11/18 12:20, Christoph Müllner wrote: >> Hi Kyrill, >> >> > On 08.11.2018, at 11:16, Kyrill Tkachov >> > wrote: >> > >> > Hi Christoph, >> > >> > On 07/11/18 21:51, christoph.muell...@theobroma-systems.com wrote: >

Re: [PATCH] [aarch64] Correct the maximum shift amount for shifted operands.

Hi Christoph, On 08/11/18 12:20, Christoph Müllner wrote: Hi Kyrill, > On 08.11.2018, at 11:16, Kyrill Tkachov wrote: > > Hi Christoph, > > On 07/11/18 21:51, christoph.muell...@theobroma-systems.com wrote: >> From: Christoph Muellner >> >> The aarch64 ISA specification allows a left shift am

Re: [PATCH] [aarch64] Correct the maximum shift amount for shifted operands.

Hi Kyrill, > On 08.11.2018, at 11:16, Kyrill Tkachov wrote: > > Hi Christoph, > > On 07/11/18 21:51, christoph.muell...@theobroma-systems.com wrote: >> From: Christoph Muellner >> >> The aarch64 ISA specification allows a left shift amount to be applied >> after extension in the range of 0 to

Re: [PATCH] [aarch64] Correct the maximum shift amount for shifted operands.

Hi Christoph, On 07/11/18 21:51, christoph.muell...@theobroma-systems.com wrote: From: Christoph Muellner The aarch64 ISA specification allows a left shift amount to be applied after extension in the range of 0 to 4 (encoded in the imm3 field). Indeed. That looks correct from my reading of

[PATCH] [aarch64] Correct the maximum shift amount for shifted operands.

From: Christoph Muellner The aarch64 ISA specification allows a left shift amount to be applied after extension in the range of 0 to 4 (encoded in the imm3 field). This is true for at least the following instructions: * ADD (extend register) * ADDS (extended register) * SUB (extended registe