Re: [PATCH] [RS6000] Change maddld match_operand from DI to GPR

2019-06-25 Thread Li Jia He
On 2019/6/24 3:38 PM, Segher Boessenkool wrote: Hi Lijia, On Mon, Jun 24, 2019 at 01:00:05AM -0500, Li Jia He wrote: >From PowerPC ISA3.0, the description of `maddld RT, RA.RB, RC` is as follows: 64-bit RA and RB are multiplied and then the RC is signed extend to 128 bits, and add them toget

Re: [PATCH] [RS6000] Change maddld match_operand from DI to GPR

2019-06-24 Thread Segher Boessenkool
On Mon, Jun 24, 2019 at 03:49:35PM +0800, Kewen.Lin wrote: > > It sounds like we can have a clean up for some others like > > TARGET_EXTSWSLI. :) > > Sorry, maybe not, it's not similar to maddld for 32bit operations. Hey, it currently is (define_insn_and_split "ashdi3_extswsli" [(set (match_o

Re: [PATCH] [RS6000] Change maddld match_operand from DI to GPR

2019-06-24 Thread Kewen.Lin
Hi Segher, on 2019/6/24 下午4:02, Segher Boessenkool wrote: > Hi Kewen, > > On Mon, Jun 24, 2019 at 03:43:26PM +0800, Kewen.Lin wrote: >> on 2019/6/24 下午3:19, Segher Boessenkool wrote: >>> Newer ISAs require 64-bit to be implemented. There are no optional >>> 64-bit categories anymore. Since this

Re: [PATCH] [RS6000] Change maddld match_operand from DI to GPR

2019-06-24 Thread Segher Boessenkool
Hi Kewen, On Mon, Jun 24, 2019 at 03:43:26PM +0800, Kewen.Lin wrote: > on 2019/6/24 下午3:19, Segher Boessenkool wrote: > > Newer ISAs require 64-bit to be implemented. There are no optional > > 64-bit categories anymore. Since this instruction is enabled for P9 > > (ISA 3.0) only (that's the TARG

Re: [PATCH] [RS6000] Change maddld match_operand from DI to GPR

2019-06-24 Thread Kewen.Lin
on 2019/6/24 下午3:43, Kewen.Lin wrote: > on 2019/6/24 下午3:19, Segher Boessenkool wrote: >> On Mon, Jun 24, 2019 at 02:45:09PM +0800, Kewen.Lin wrote: >>> on 2019/6/24 下午2:00, Li Jia He wrote: -#define TARGET_MADDLD (TARGET_MODULO && TARGET_POWERPC64) +#define TARGET_MADDLD TARGET

Re: [PATCH] [RS6000] Change maddld match_operand from DI to GPR

2019-06-24 Thread Kewen.Lin
on 2019/6/24 下午3:19, Segher Boessenkool wrote: > On Mon, Jun 24, 2019 at 02:45:09PM +0800, Kewen.Lin wrote: >> on 2019/6/24 下午2:00, Li Jia He wrote: >>> -#define TARGET_MADDLD (TARGET_MODULO && TARGET_POWERPC64) >>> +#define TARGET_MADDLD TARGET_MODULO >> >> IMHO, I don't think this remov

Re: [PATCH] [RS6000] Change maddld match_operand from DI to GPR

2019-06-24 Thread Segher Boessenkool
Hi Lijia, On Mon, Jun 24, 2019 at 01:00:05AM -0500, Li Jia He wrote: > >From PowerPC ISA3.0, the description of `maddld RT, RA.RB, RC` is as follows: > 64-bit RA and RB are multiplied and then the RC is signed extend to 128 bits, > and add them together. > > We only apply it to 64-bit mode (DI) w

Re: [PATCH] [RS6000] Change maddld match_operand from DI to GPR

2019-06-24 Thread Segher Boessenkool
On Mon, Jun 24, 2019 at 02:45:09PM +0800, Kewen.Lin wrote: > on 2019/6/24 下午2:00, Li Jia He wrote: > > -#define TARGET_MADDLD (TARGET_MODULO && TARGET_POWERPC64) > > +#define TARGET_MADDLD TARGET_MODULO > > IMHO, I don't think this removal of TARGET_POWERPC64 is reasonable. > As ISA V3.0

Re: [PATCH] [RS6000] Change maddld match_operand from DI to GPR

2019-06-23 Thread Kewen.Lin
Hi Lijia, on 2019/6/24 下午2:00, Li Jia He wrote: > Hi, > > From PowerPC ISA3.0, the description of `maddld RT, RA.RB, RC` is as follows: > 64-bit RA and RB are multiplied and then the RC is signed extend to 128 bits, > and add them together. > > We only apply it to 64-bit mode (DI) when implement

[PATCH] [RS6000] Change maddld match_operand from DI to GPR

2019-06-23 Thread Li Jia He
Hi, >From PowerPC ISA3.0, the description of `maddld RT, RA.RB, RC` is as follows: 64-bit RA and RB are multiplied and then the RC is signed extend to 128 bits, and add them together. We only apply it to 64-bit mode (DI) when implementing maddld. However, if we can guarantee that the result of t