On 2020/7/13 上午8:32, Jim Wilson wrote:
This looks like a security leak that the canary value is left in a4.
The i386 implementation operates directly on memory without loading
into registers. The rs6000 implementation is careful to load 0 into
the other register in the stack_protector_test cod
On Tue, Jul 7, 2020 at 7:51 PM cooper wrote:
> gcc/
> * config/riscv/riscv-opts.h (stack_protector_guard): New enum.
> * config/riscv/riscv.c (riscv_option_override): Handle
> the new options.
> * config/riscv/riscv.md (stack_protect_set): New pattern to handle
>
Hi Cooper,
Great Job!
Tested-by: Guo Ren
Here is kernel related patch with tested result:
https://lore.kernel.org/linux-riscv/1594279697-72511-2-git-send-email-guo...@kernel.org/T/#u
Best Regards
Guo Ren
On 2020/7/8 上午10:51, cooper wrote:
The linux kernel guys are discussing about supp
The linux kernel guys are discussing about supporting TLS register based
stack proctector canary, the link is as follows:
https://lore.kernel.org/linux-riscv/202007051820.DABE7F87D7@keescook/T/#t
I implemented register based stack protector canary with reference to
aarch64 and x86. When ad
