t; -Original Message-
>>>> From: Richard Biener
>>>> Sent: Friday, October 11, 2024 7:52 AM
>>>> To: Richard Sandiford
>>>> Cc: Jennifer Schmitz ; gcc-patches@gcc.gnu.org;
>>>> Richard
>>>> Earnshaw ; Kyrylo Tkachov
>&
M
>>> To: Richard Sandiford
>>> Cc: Jennifer Schmitz ; gcc-patches@gcc.gnu.org; Richard
>>> Earnshaw ; Kyrylo Tkachov
>>> ; Tamar Christina
>>> Subject: Re: [PATCH][PR113816] AArch64: Use SIMD+GPR for logical vector
>>> reductions
>>
: Re: [PATCH][PR113816] AArch64: Use SIMD+GPR for logical vector
reductions
On Thu, 10 Oct 2024, Richard Sandiford wrote:
Jennifer Schmitz writes:
This patch implements the optabs reduc_and_scal_,
reduc_ior_scal_, and reduc_xor_scal_ for ASIMD modes V8QI,
V16QI, V4HI, and V8HI for TARGET_SIMD to
hristina
>> Subject: Re: [PATCH][PR113816] AArch64: Use SIMD+GPR for logical vector
>> reductions
>>
>> On Thu, 10 Oct 2024, Richard Sandiford wrote:
>>
>> > Jennifer Schmitz writes:
>> > > This patch implements the optabs reduc_and_scal_,
>&
v
> > ; Tamar Christina
> > Subject: Re: [PATCH][PR113816] AArch64: Use SIMD+GPR for logical vector
> > reductions
> >
> > On Thu, 10 Oct 2024, Richard Sandiford wrote:
> >
> > > Jennifer Schmitz writes:
> > > > This patch implements
> -Original Message-
> From: Richard Biener
> Sent: Friday, October 11, 2024 7:52 AM
> To: Richard Sandiford
> Cc: Jennifer Schmitz ; gcc-patches@gcc.gnu.org; Richard
> Earnshaw ; Kyrylo Tkachov
> ; Tamar Christina
> Subject: Re: [PATCH][PR113816] AArch64:
On Thu, 10 Oct 2024, Richard Sandiford wrote:
> Jennifer Schmitz writes:
> > This patch implements the optabs reduc_and_scal_,
> > reduc_ior_scal_, and reduc_xor_scal_ for ASIMD modes V8QI,
> > V16QI, V4HI, and V8HI for TARGET_SIMD to improve codegen for bitwise logical
> > vector reduction opera
.@suse.de
>> Subject: Re: [PATCH][PR113816] AArch64: Use SIMD+GPR for logical vector
>> reductions
>>
>> Jennifer Schmitz writes:
>> > This patch implements the optabs reduc_and_scal_,
>> > reduc_ior_scal_, and reduc_xor_scal_ for ASIMD modes V8QI,
>
> -Original Message-
> From: Richard Sandiford
> Sent: Thursday, October 10, 2024 8:08 PM
> To: Jennifer Schmitz
> Cc: gcc-patches@gcc.gnu.org; Richard Earnshaw ;
> Kyrylo Tkachov ; Tamar Christina
> ; rguent...@suse.de
> Subject: Re: [PATCH][PR113816] AArch64:
Jennifer Schmitz writes:
> This patch implements the optabs reduc_and_scal_,
> reduc_ior_scal_, and reduc_xor_scal_ for ASIMD modes V8QI,
> V16QI, V4HI, and V8HI for TARGET_SIMD to improve codegen for bitwise logical
> vector reduction operations.
> Previously, either only vector registers or only
Hi Jennifer,
> -Original Message-
> From: Jennifer Schmitz
> Sent: Thursday, October 10, 2024 9:27 AM
> To: gcc-patches@gcc.gnu.org
> Cc: Richard Sandiford ; Richard Earnshaw
> ; Kyrylo Tkachov ; Tamar
> Christina
> Subject: [PATCH][PR113816] AArch64: Use SIM
This patch implements the optabs reduc_and_scal_,
reduc_ior_scal_, and reduc_xor_scal_ for ASIMD modes V8QI,
V16QI, V4HI, and V8HI for TARGET_SIMD to improve codegen for bitwise logical
vector reduction operations.
Previously, either only vector registers or only general purpose registers (GPR)
wer
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