Re: [PATCH][ARM] Tie operand 1 to operand 0 in AESMC pattern when fusing AES/AESMC

2016-06-01 Thread Ramana Radhakrishnan
On 27/05/16 14:46, Kyrill Tkachov wrote: > > On 20/05/16 11:04, Kyrill Tkachov wrote: >> Hi all, >> >> The recent -frename-registers change exposed a deficiency in the way we fuse >> AESE/AESMC instruction >> pairs in arm. >> >> Basically we want to enforce: >> AESE Vn, _ >> AESMC Vn, V

Re: [PATCH][ARM] Tie operand 1 to operand 0 in AESMC pattern when fusing AES/AESMC

2016-05-27 Thread Kyrill Tkachov
On 20/05/16 11:04, Kyrill Tkachov wrote: Hi all, The recent -frename-registers change exposed a deficiency in the way we fuse AESE/AESMC instruction pairs in arm. Basically we want to enforce: AESE Vn, _ AESMC Vn, Vn to enable the fusion, but regrename comes along and renames the out

[PATCH][ARM] Tie operand 1 to operand 0 in AESMC pattern when fusing AES/AESMC

2016-05-20 Thread Kyrill Tkachov
Hi all, The recent -frename-registers change exposed a deficiency in the way we fuse AESE/AESMC instruction pairs in arm. Basically we want to enforce: AESE Vn, _ AESMC Vn, Vn to enable the fusion, but regrename comes along and renames the output Vn register in AESMC to something else