On Thu, Jun 07, 2018 at 05:58:01AM -0500, Kyrill Tkachov wrote:
>
> On 05/06/18 18:28, James Greenhalgh wrote:
> > On Tue, Jun 05, 2018 at 11:32:06AM -0500, Kyrill Tkachov wrote:
> >> On 04/06/18 18:40, Kyrill Tkachov wrote:
> >>> Hi all,
> >>>
> >>> This patch adds support for generating LDPs and
On 05/06/18 18:28, James Greenhalgh wrote:
On Tue, Jun 05, 2018 at 11:32:06AM -0500, Kyrill Tkachov wrote:
On 04/06/18 18:40, Kyrill Tkachov wrote:
Hi all,
This patch adds support for generating LDPs and STPs of Q-registers.
This allows for more compact code generation and makes better use of
> On 5 Jun 2018, at 19:28, James Greenhalgh wrote:
>
> On Tue, Jun 05, 2018 at 11:32:06AM -0500, Kyrill Tkachov wrote:
>>
>> On 04/06/18 18:40, Kyrill Tkachov wrote:
>>> Hi all,
>>>
>>> This patch adds support for generating LDPs and STPs of Q-registers.
>>> This allows for more compact code g
On Tue, Jun 05, 2018 at 11:32:06AM -0500, Kyrill Tkachov wrote:
>
> On 04/06/18 18:40, Kyrill Tkachov wrote:
> > Hi all,
> >
> > This patch adds support for generating LDPs and STPs of Q-registers.
> > This allows for more compact code generation and makes better use of the
> > ISA.
> >
> > It's
On 06/05/2018 10:02 PM, Kyrill Tkachov wrote:
Adding some folks who know more about other CPUs as well.
Are you okay with enabling these instructions in AArch64?
If you could give this a spin on some benchmarks you
care about on your platforms it would be really useful data.
Sameera had writte
On Tue, Jun 5, 2018 at 9:32 AM Kyrill Tkachov
wrote:
>
>
> On 04/06/18 18:40, Kyrill Tkachov wrote:
> > Hi all,
> >
> > This patch adds support for generating LDPs and STPs of Q-registers.
> > This allows for more compact code generation and makes better use of the
> > ISA.
> >
> > It's implement
On 04/06/18 18:40, Kyrill Tkachov wrote:
Hi all,
This patch adds support for generating LDPs and STPs of Q-registers.
This allows for more compact code generation and makes better use of the ISA.
It's implemented in a straightforward way by allowing 16-byte modes in the
sched-fusion machinery
Hi all,
This patch adds support for generating LDPs and STPs of Q-registers.
This allows for more compact code generation and makes better use of the ISA.
It's implemented in a straightforward way by allowing 16-byte modes in the
sched-fusion machinery and adding appropriate peepholes in aarch64
