Re: [PATCH][AArch64] Change representation of SABD in RTL

2019-02-07 Thread Kyrill Tkachov
Hi James, On 06/02/19 17:33, James Greenhalgh wrote: On Mon, Feb 04, 2019 at 04:23:32AM -0600, Kyrill Tkachov wrote: Hi all, Richard raised a concern about the RTL we use to represent the AdvSIMD SABD (vector signed absolute difference) instruction. We currently represent it as ABS (MINUS op1

Re: [PATCH][AArch64] Change representation of SABD in RTL

2019-02-06 Thread James Greenhalgh
On Mon, Feb 04, 2019 at 04:23:32AM -0600, Kyrill Tkachov wrote: > Hi all, > > Richard raised a concern about the RTL we use to represent the AdvSIMD SABD > (vector signed absolute difference) instruction. > We currently represent it as ABS (MINUS op1 op2). > > This isn't exactly what SABD does. A

[PATCH][AArch64] Change representation of SABD in RTL

2019-02-04 Thread Kyrill Tkachov
Hi all, Richard raised a concern about the RTL we use to represent the AdvSIMD SABD (vector signed absolute difference) instruction. We currently represent it as ABS (MINUS op1 op2). This isn't exactly what SABD does. ABS treats its input as a signed value and returns the absolute of that. For