Re: [PATCH][AArch64] Allow multiple-of-8 immediate offsets for TImode LDP/STP

2016-08-01 Thread Richard Earnshaw (lists)
On 13/07/16 17:14, Kyrill Tkachov wrote: > Hi all, > > The most common way to load and store TImode value in aarch64 is to > perform an LDP/STP of two X-registers. > This is the *movti_aarch64 pattern in aarch64.md. > There is a bug in the logic in aarch64_classify_address where it > validates the

Re: [PATCH][AArch64] Allow multiple-of-8 immediate offsets for TImode LDP/STP

2016-08-01 Thread Kyrill Tkachov
Ping. https://gcc.gnu.org/ml/gcc-patches/2016-07/msg00737.html Thanks, Kyrill On 13/07/16 17:14, Kyrill Tkachov wrote: Hi all, The most common way to load and store TImode value in aarch64 is to perform an LDP/STP of two X-registers. This is the *movti_aarch64 pattern in aarch64.md. There is

Re: [PATCH][AArch64] Allow multiple-of-8 immediate offsets for TImode LDP/STP

2016-07-13 Thread Evandro Menezes
On 07/13/16 11:14, Kyrill Tkachov wrote: Hi all, The most common way to load and store TImode value in aarch64 is to perform an LDP/STP of two X-registers. This is the *movti_aarch64 pattern in aarch64.md. There is a bug in the logic in aarch64_classify_address where it validates the offset i

[PATCH][AArch64] Allow multiple-of-8 immediate offsets for TImode LDP/STP

2016-07-13 Thread Kyrill Tkachov
Hi all, The most common way to load and store TImode value in aarch64 is to perform an LDP/STP of two X-registers. This is the *movti_aarch64 pattern in aarch64.md. There is a bug in the logic in aarch64_classify_address where it validates the offset in the address used to load a TImode value.