RE: [PATCH][AArch64] Add separate insn sched class for vector LDP & STP

2015-10-01 Thread Evandro Menezes
o Menezes > Cc: gcc-patches; James Greenhalgh; Marcus Shawcroft; Philipp Tomsich > Subject: Re: [PATCH][AArch64] Add separate insn sched class for vector LDP & > STP > > On Tue, Sep 29, 2015 at 12:52 AM, Evandro Menezes > wrote: > > In some micro-architectures the in

Re: [PATCH][AArch64] Add separate insn sched class for vector LDP & STP

2015-09-29 Thread Ramana Radhakrishnan
On Tue, Sep 29, 2015 at 12:52 AM, Evandro Menezes wrote: > In some micro-architectures the insns to load or store pairs of vector > registers are implemented rather differently from those affecting lanes in > vector registers. Then, it's important that such insns be described > likewise different

RE: [PATCH][AArch64] Add separate insn sched class for vector LDP & STP

2015-09-29 Thread Evandro Menezes
; Evandro Menezes; gcc-patches@gcc.gnu.org > Cc: James Greenhalgh; Ramana Radhakrishnan > Subject: Re: [PATCH][AArch64] Add separate insn sched class for vector LDP & > STP > > > On 29/09/15 09:03, Marcus Shawcroft wrote: > > On 29/09/15 00:52, Evandro Menezes wrote:

Re: [PATCH][AArch64] Add separate insn sched class for vector LDP & STP

2015-09-29 Thread Kyrill Tkachov
ector-LDP.patch From 340249dcd2af8dfce486cb4f62d4eaf285c6a799 Mon Sep 17 00:00:00 2001 From: Evandro Menezes Date: Mon, 28 Sep 2015 15:00:00 -0500 Subject: [PATCH] [AArch64] Add separate insn sched class for vector LDP & STP 2015-09-28 Evandro Menezes gcc/ * config/arm

Re: [PATCH][AArch64] Add separate insn sched class for vector LDP & STP

2015-09-29 Thread Marcus Shawcroft
andro Menezes 0001-AArch64-Add-separate-insn-sched-class-for-vector-LDP.patch From 340249dcd2af8dfce486cb4f62d4eaf285c6a799 Mon Sep 17 00:00:00 2001 From: Evandro Menezes Date: Mon, 28 Sep 2015 15:00:00 -0500 Subject: [PATCH] [AArch64] Add separate insn sched class for vector LDP & STP 2

Re: [PATCH][AArch64] Add separate insn sched class for vector LDP & STP

2015-09-28 Thread Andrew Pinski
On Mon, Sep 28, 2015 at 4:52 PM, Evandro Menezes wrote: > In some micro-architectures the insns to load or store pairs of vector > registers are implemented rather differently from those affecting lanes in > vector registers. Then, it's important that such insns be described > likewise differentl

[PATCH][AArch64] Add separate insn sched class for vector LDP & STP

2015-09-28 Thread Evandro Menezes
: [PATCH] [AArch64] Add separate insn sched class for vector LDP & STP 2015-09-28 Evandro Menezes gcc/ * config/arm/types.md (neon_ldp, neon_ldp_q, neon_stp, neon_stp_q): add new insn types for vector load and store pairs. * config/arm/cortex-a53.md (cortex_a53_f_load_2reg): add