"Andre Vieira (lists)" writes:
> Hi,
>
> Using aarch64_pred_mov for these was tricky as it did both store and
> load. Furthermore there was some concern it might allow for a predicated
> mov to end up as a mem -> mem and a predicated load being wrongfully
> reloaded to a full-load to register.
Hi,
Using aarch64_pred_mov for these was tricky as it did both store and
load. Furthermore there was some concern it might allow for a predicated
mov to end up as a mem -> mem and a predicated load being wrongfully
reloaded to a full-load to register. So instead we decided to let the
extendin
"Andre Vieira (lists)" writes:
> Hi,
>
> I noticed we were missing out on LD1 + UXT combinations in some cases
> and found it was because of inconsistent use of the unspec enum
> UNSPEC_LD1_SVE. The combine pattern for LD1[S][BHWD] uses UNSPEC_LD1_SVE
> whereas one of the LD1 expanders was usin
Hi,
I noticed we were missing out on LD1 + UXT combinations in some cases
and found it was because of inconsistent use of the unspec enum
UNSPEC_LD1_SVE. The combine pattern for LD1[S][BHWD] uses UNSPEC_LD1_SVE
whereas one of the LD1 expanders was using UNSPEC_PRED_X. I wasn't sure
whether to
