On Mon, Sep 19, 2016 at 06:20:59PM -0500, Segher Boessenkool wrote:
> On Mon, Sep 19, 2016 at 06:51:42PM -0400, Michael Meissner wrote:
> > > > However ISA 2.07 (i.e. power8) added the VMRGEW instruction, which can
> > > > do this
> > > > more simply:
> > > >
> > > > xxpermdi 34,1,2,0
> >
On Mon, Sep 19, 2016 at 06:51:42PM -0400, Michael Meissner wrote:
> > > However ISA 2.07 (i.e. power8) added the VMRGEW instruction, which can do
> > > this
> > > more simply:
> > >
> > > xxpermdi 34,1,2,0
> > > xxpermdi 32,3,4,0
> > > xvcvdpsp 34,34
> > > xvcvdpsp
On Mon, Sep 19, 2016 at 05:43:19PM -0500, Segher Boessenkool wrote:
> On Mon, Sep 19, 2016 at 06:02:08PM -0400, Michael Meissner wrote:
> > vector float combine (float a, float b, float c, float d)
> > {
> > return (vector float) { a, b, c, d };
> > }
>
> [ ... ]
>
> > However ISA 2.07 (i.e. po
On Mon, Sep 19, 2016 at 06:02:08PM -0400, Michael Meissner wrote:
> vector float combine (float a, float b, float c, float d)
> {
> return (vector float) { a, b, c, d };
> }
[ ... ]
> However ISA 2.07 (i.e. power8) added the VMRGEW instruction, which can do this
> more simply:
>
> xxpe
The original VSX instruction set did not have a simple way to merge the two
vectors with the upper words set in each double word that hold the float values
in V4SFmode format after the XVCVDPSP instructions. So, the code used a VPERM
instruction to reorder the parts.
vector float combine (float a
