On Tue, Sep 26, 2017 at 06:37:17PM -0400, Michael Meissner wrote:
> On Tue, Sep 26, 2017 at 04:56:54PM -0500, Segher Boessenkool wrote:
> > On Tue, Sep 26, 2017 at 10:48:29AM -0400, Michael Meissner wrote:
> > > * config/rs6000/vsx.md (peephole for optimizing move SF to GPR):
> > > Adjust code
On Tue, Sep 26, 2017 at 04:56:54PM -0500, Segher Boessenkool wrote:
> On Tue, Sep 26, 2017 at 10:48:29AM -0400, Michael Meissner wrote:
> > * config/rs6000/vsx.md (peephole for optimizing move SF to GPR):
> > Adjust code to eliminate needing to do the shift right 32-bits
> > operation a
On Tue, Sep 26, 2017 at 10:48:29AM -0400, Michael Meissner wrote:
> * config/rs6000/vsx.md (peephole for optimizing move SF to GPR):
> Adjust code to eliminate needing to do the shift right 32-bits
> operation after XSCVDPSPN.
After staring at this way too long... Looks correct.
On Tue, Sep 26, 2017 at 11:36:14AM -0500, Segher Boessenkool wrote:
> Hi!
>
> On Tue, Sep 26, 2017 at 10:34:44AM -0400, Michael Meissner wrote:
> > * config/rs6000/rs6000.md (movsi_from_df): Optimize converting a
> > DFmode to a SFmode, and then needing to move the SFmode to a GPR
> >
On Tue, Sep 26, 2017 at 11:06:09AM -0500, Segher Boessenkool wrote:
> > @@ -6850,52 +6850,41 @@ (define_insn_and_split "movsi_from_sf"
> >rtx op1 = operands[1];
> >rtx op2 = operands[2];
> >rtx op0_di = gen_rtx_REG (DImode, REGNO (op0));
> > + rtx op2_si = gen_rtx_REG (SImode, REGNO (o
On Tue, Sep 26, 2017 at 10:50:14AM -0400, Michael Meissner wrote:
> * gcc.target/powerpc/pr71977-1.c: Update test to know that we
> don't generate a 32-bit shift after doing XSCVDPSPN.
> * gcc.target/powerpc/direct-move-float1.c: Likewise.
> * gcc.target/powerpc/direct-move-
On Tue, Sep 26, 2017 at 10:44:24AM -0400, Michael Meissner wrote:
> * config/rs6000/vsx.md (vsx_xscvdpspn): Eliminate useless
> alternative constraint.
> (vsx_xscvspdpn): Likewise.
> (vsx_xscvspdpn_scalar): Likewise.
Okay, nice cleanup! Thanks,
Segher
Hi!
On Tue, Sep 26, 2017 at 10:39:06AM -0400, Michael Meissner wrote:
> * config/rs6000/vsx.md (vsx_xscvdpsp_scalar): Use "ww" constraint
> instead of "f" to allow SFmode to be in traditional Altivec
> registers.
Okay. Thanks,
Segher
On Tue, Sep 26, 2017 at 10:36:34AM -0400, Michael Meissner wrote:
> * config/rs6000/vsx.md (vsx_xscvspdp_scalar2): Move insn so that
> it is adjacent to the other XSCVSPDP insns.
Okay for trunk. Thanks,
Segher
Hi!
On Tue, Sep 26, 2017 at 10:34:44AM -0400, Michael Meissner wrote:
> * config/rs6000/rs6000.md (movsi_from_df): Optimize converting a
> DFmode to a SFmode, and then needing to move the SFmode to a GPR
> to use the XSCVDPSP instruction instead of FRSP and XSCVDPSPN.
> --- gcc/
Hi,
On Tue, Sep 26, 2017 at 10:32:03AM -0400, Michael Meissner wrote:
> * config/rs6000/rs6000.md (movsi_from_sf): Adjust code to
> eliminate doing a 32-bit shift right or vector extract after doing
> XSCVDPSPN. Use zero_extendsidi2 instead of p8_mfvsrd_4_disf to
> move th
Hi!
On Tue, Sep 26, 2017 at 10:30:03AM -0400, Michael Meissner wrote:
> I have broken the patches down to 8 chunks.
Thanks for doing this.
> +(define_split
> + [(set (match_operand:DI 0 "int_reg_operand")
> + (sign_extend:DI (match_operand:SI 1 "vsx_register_operand")))]
Should be EXTSI in
Off list, Segher asked that I break the patch eliminating a shift right when
transfering SFmode from a vector register to a GPR register down into smaller
chunks. The power7 and power8 instructions that convert values in the double
precision format to single precision actually duplicate the 32-bit
Off list, Segher asked that I break the patch eliminating a shift right when
transfering SFmode from a vector register to a GPR register down into smaller
chunks. The power7 and power8 instructions that convert values in the double
precision format to single precision actually duplicate the 32-bit
Off list, Segher asked that I break the patch eliminating a shift right when
transfering SFmode from a vector register to a GPR register down into smaller
chunks. The power7 and power8 instructions that convert values in the double
precision format to single precision actually duplicate the 32-bit
Off list, Segher asked that I break the patch eliminating a shift right when
transfering SFmode from a vector register to a GPR register down into smaller
chunks. The power7 and power8 instructions that convert values in the double
precision format to single precision actually duplicate the 32-bit
Off list, Segher asked that I break the patch eliminating a shift right when
transfering SFmode from a vector register to a GPR register down into smaller
chunks. The power7 and power8 instructions that convert values in the double
precision format to single precision actually duplicate the 32-bit
Off list, Segher asked that I break the patch eliminating a shift right when
transfering SFmode from a vector register to a GPR register down into smaller
chunks. The power7 and power8 instructions that convert values in the double
precision format to single precision actually duplicate the 32-bit
Off list, Segher asked that I break the patch eliminating a shift right when
transfering SFmode from a vector register to a GPR register down into smaller
chunks. The power7 and power8 instructions that convert values in the double
precision format to single precision actually duplicate the 32-bit
Off list, Segher asked that I break the patch eliminating a shift right when
transfering SFmode from a vector register to a GPR register down into smaller
chunks. The power7 and power8 instructions that convert values in the double
precision format to single precision actually duplicate the 32-bit
On the PowerPC starting with ISA 2.07 (power8), moving a single precision value
(SFmode) from a vector register to a GPR involves converting the scalar value
in the register from being in double (DFmode) format to the 32-bit
vector/storage format, doing the move to the GPR, and then doing a shift r
21 matches
Mail list logo
