> Catherine Moore writes:
> >
> > gcc/testsuite/ChangeLog:
> >
> > * gcc.target/mips/msa-builtins.c (dg-final): Tweak regex for the
> > 32-bit
> > insert.d case.
>
> Please change to:
> * gcc.target/mips-msa-builtins.c (msa_insert_d): Tweak expected
> output.
>
> Okay with that chan
> -Original Message-
> From: Toma Tabacu [mailto:toma.tab...@imgtec.com]
> Sent: Thursday, December 15, 2016 9:51 AM
> To: gcc-patches@gcc.gnu.org
> Cc: Matthew Fortune ; Moore,
> Catherine
> Subject: [PATCH, testsuite] MIPS: Relax instruction order check in msa-
Hi,
The 32-bit insert.d case in msa-builtins.c is failing with O2 and Os because
the order of the emitted instructions is slightly different compared to the
other optimization levels.
This patch tweaks the regular expression for 32-bit insert.d to accept the
alternate instruction order.
Tested
