On 9/25/20 6:50 PM, Segher Boessenkool wrote:
On Fri, Sep 25, 2020 at 03:34:49PM -0500, will schmidt wrote:
On Fri, 2020-09-25 at 12:36 -0500, Segher Boessenkool wrote:
No, it cannot.
This is used for pdepd/pextd/cntlzdm/cnttzdm/cfuged, all of which do
need 64-bit registers to do anything sane
On Fri, Sep 25, 2020 at 03:34:49PM -0500, will schmidt wrote:
> On Fri, 2020-09-25 at 12:36 -0500, Segher Boessenkool wrote:
> > No, it cannot.
> >
> > This is used for pdepd/pextd/cntlzdm/cnttzdm/cfuged, all of which do
> > need 64-bit registers to do anything sane.
> >
> > This should really ha
On Fri, 2020-09-25 at 12:36 -0500, Segher Boessenkool wrote:
> Hi!
>
> On Thu, Sep 24, 2020 at 03:35:24PM -0500, will schmidt wrote:
> > We have extraneous BTM entry (RS6000_BTM_POWERPC64) in the
> > define for
> > our P10 MISC 2 builtin definition. This does not exist for the
> > '0',
> > '1
Hi!
On Thu, Sep 24, 2020 at 03:35:24PM -0500, will schmidt wrote:
> We have extraneous BTM entry (RS6000_BTM_POWERPC64) in the define for
> our P10 MISC 2 builtin definition. This does not exist for the '0',
> '1' or '3' definitions. It appears to me that this was erroneously
> copied from th
[PATCH, rs6000] correct an erroneous blip in the BU_P10_MISC define
Hi,
We have extraneous BTM entry (RS6000_BTM_POWERPC64) in the define for
our P10 MISC 2 builtin definition. This does not exist for the '0',
'1' or '3' definitions. It appears to me that this was erroneously
copied from the
