David Edelsohn wrote:
> On Mon, Nov 18, 2013 at 3:07 PM, Ulrich Weigand wrote:
> > Also note that this patch does not change how TDmode values are loaded
> > into GPRs: on little-endian, this means we do get the usual LE subreg
> > order there (least significant word in lowest-numbered register).
On Mon, Nov 18, 2013 at 3:07 PM, Ulrich Weigand wrote:
> Also note that this patch does not change how TDmode values are loaded
> into GPRs: on little-endian, this means we do get the usual LE subreg
> order there (least significant word in lowest-numbered register). This
> does still seem the
Hello,
when loading a TDmode value into floating-point registers, they need to go
into a register pair with the even register holding the most significant
word and the odd register holding the least significant word, because this
is what the instruction set expects. This hold for both big-endian
