On Mon, May 10, 2021 at 08:53:31AM -0500, Peter Bergner wrote:
> On 5/10/21 7:52 AM, Pat Haugen wrote:
> > On 5/7/21 6:00 PM, Segher Boessenkool wrote:
> >> So what is this replaced with? Was it an "xxlmr" and it is just
> >> unnecessary now?
> >
> > Different RA choice made the reg copy unnecess
On 5/10/21 7:52 AM, Pat Haugen wrote:
> On 5/7/21 6:00 PM, Segher Boessenkool wrote:
>> So what is this replaced with? Was it an "xxlmr" and it is just
>> unnecessary now?
>
> Different RA choice made the reg copy unnecessary.
>
> < xxspltib 0,8
> < xxlor 32,0,0
> ---
>> xxspltib 32
On 5/7/21 6:00 PM, Segher Boessenkool wrote:
>> --- a/gcc/testsuite/gcc.target/powerpc/vec-rlmi-rlnm.c
>> +++ b/gcc/testsuite/gcc.target/powerpc/vec-rlmi-rlnm.c
>> @@ -62,6 +62,6 @@ rlnm_test_2 (vector unsigned long long x, vector unsigned
>> long long y,
>> /* { dg-final { scan-assembler-times "
Hi!
On Fri, May 07, 2021 at 10:53:31AM -0500, Pat Haugen wrote:
> Code that has heavy register pressure on Altivec registers can suffer from
> over-aggressive scheduling during sched1, which then leads to increased
> register spill. This is due to the fact that registers that prefer
> ALTIVEC_REGS
Add ALTIVEC_REGS as pressure class.
Code that has heavy register pressure on Altivec registers can suffer from
over-aggressive scheduling during sched1, which then leads to increased
register spill. This is due to the fact that registers that prefer
ALTIVEC_REGS are currently assigned an allocno c
