On Mon, 2017-10-23 at 16:21 -0500, Segher Boessenkool wrote:
> Hi!
>
> On Tue, Oct 17, 2017 at 01:24:45PM -0500, Steven Munroe wrote:
> > Some inline assembler is required. There a several cases where we need
> > to generate Data Cache Block instruction. There are no existing builtin
> > for flus
Hi!
On Tue, Oct 17, 2017 at 01:24:45PM -0500, Steven Munroe wrote:
> Some inline assembler is required. There a several cases where we need
> to generate Data Cache Block instruction. There are no existing builtin
> for flush and touch for store transient.
Would builtins for those help? Would a
These is the forth major contribution of X86 intrinsic equivalent
headers for PPC64LE.
X86 SSE2 technology adds double float (__m128d) support, filled in a
number 128-bit vector integer (__m128i) operations and added some MMX
conversions to and from 128-bit vector (XMM) operations.
In general the
