Hi,
> > Hi Matthew/Catherine,
> >
> > The attached patch removes the restriction to compile a TU with an ISR with
> -
> > mhard-float. Instead of forcing -msoft-float, the coprocessor 1 is disabled
> in
> > an ISR for -mhard-float.
> >
> > Ok to apply?
>
> Yes, this one is OK.
Committed as r2258
> -Original Message-
> From: Robert Suchanek [mailto:robert.sucha...@imgtec.com]
> Sent: Wednesday, July 08, 2015 6:42 AM
> To: Matthew Fortune; Moore, Catherine; gcc-patches@gcc.gnu.org
> Subject: [PATCH, MIPS] Support interrupt handlers with hard-float
>
>
Hi Matthew/Catherine,
The attached patch removes the restriction to compile a TU with an ISR with
-mhard-float. Instead of forcing -msoft-float, the coprocessor 1 is disabled in
an ISR for -mhard-float.
Ok to apply?
Regards,
Robert
gcc/
* config/mips/mips.c (mips_compute_frame_info):
