Richard Sandiford writes:
> Matthew Fortune writes:
> > diff --git a/gcc/testsuite/gcc.target/mips/oddspreg-6.c
> b/gcc/testsuite/gcc.target/mips/oddspreg-6.c
> > new file mode 100644
> > index 000..2d1b129
> > --- /dev/null
> > +++ b/gcc/testsuite/gcc.target/mips/oddspreg-6.c
> > @@ -0,0 +1,
Matthew Fortune writes:
> diff --git a/gcc/testsuite/gcc.target/mips/oddspreg-6.c
> b/gcc/testsuite/gcc.target/mips/oddspreg-6.c
> new file mode 100644
> index 000..2d1b129
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/mips/oddspreg-6.c
> @@ -0,0 +1,15 @@
> +/* Check that we disable odd-nu
oongson.cn]
Sent: 04 May 2014 23:38
To: Matthew Fortune; Richard Sandiford
Cc: 'gcc-patches@gcc.gnu.org' (gcc-patches@gcc.gnu.org); Rich Fuhler
Subject: Re: RE: [PATCH, MIPS] Alter default number of single-precision
registers
Hi Matthew：
Test passed on Loongson3a on the case:
void foo (v
Richard Sandiford writes:
> -march is "which instructions can I use?" and -mtune is "which
> instructions
> give good performance?". My understanding is that you wanted to disable
> the instructions for mips32r2 etc. so that they can be safely linked
> with loongson3a code, in which case it's an
Matthew Fortune writes:
> Richard Sandiford writes:
>> Matthew Fortune writes:
>> > Hi Richard,
>> >
>> > When MIPSr1 introduced the ability to use odd-numbered
>> > single-precision registers some implementations continued to only
>> > support even-numbered single-precision registers. Notably,
Richard Sandiford writes:
> Matthew Fortune writes:
> > Hi Richard,
> >
> > When MIPSr1 introduced the ability to use odd-numbered
> > single-precision registers some implementations continued to only
> > support even-numbered single-precision registers. Notably,
> loongson3a
> > in FR=0 mode on
Matthew Fortune writes:
> Hi Richard,
>
> When MIPSr1 introduced the ability to use odd-numbered single-precision
> registers some implementations continued to only support even-numbered
> single-precision registers. Notably, loongson3a in FR=0 mode only
> permits the even-numbered registers to b
Hi Richard,
When MIPSr1 introduced the ability to use odd-numbered single-precision
registers some implementations continued to only support even-numbered
single-precision registers. Notably, loongson3a in FR=0 mode only
permits the even-numbered registers to be used. For this reason and
also to
