On 30 July 2014 11:10, James Greenhalgh wrote:
> 2014-07-30 James Greenhalgh
>
> * config/aarch64/aarch64.c (aarch64_simd_vect_par_cnst_half): Vary
> the generated mask based on BYTES_BIG_ENDIAN.
> (aarch64_simd_check_vect_par_cnst_half): New.
> * config/aarch64
On Wed, Jul 30, 2014 at 11:21:40AM +0100, Richard Biener wrote:
> On Wed, Jul 30, 2014 at 12:10 PM, James Greenhalgh
> wrote:
> >
> > Hi,
> >
> > A vec_select mask exists in GCC's world-view of lane ordering. The
> > "low-half" of the vector { a, b, c, d } is { a, b }, which on big-endian
> > will
On Wed, Jul 30, 2014 at 12:10 PM, James Greenhalgh
wrote:
>
> Hi,
>
> A vec_select mask exists in GCC's world-view of lane ordering. The
> "low-half" of the vector { a, b, c, d } is { a, b }, which on big-endian
> will be in the high bits of the architectural register. On little-endian,
> these la
Hi,
A vec_select mask exists in GCC's world-view of lane ordering. The
"low-half" of the vector { a, b, c, d } is { a, b }, which on big-endian
will be in the high bits of the architectural register. On little-endian,
these lanes will be in the low bits of the architectural register.
We therefore
