Re: [AArch64] __atomic_thread_fence and release memory model

2013-02-14 Thread Yvan Roux
Oops, I missed that the release semantics is not just store before store but also load before store, sorry for that :( Yvan On 14 February 2013 16:40, Yvan Roux wrote: > Hi, > > a call to the builtin __atomic_thread_fence with the memory model > __ATOMIC_RELEASE generates a data memory barrier w

[AArch64] __atomic_thread_fence and release memory model

2013-02-14 Thread Yvan Roux
Hi, a call to the builtin __atomic_thread_fence with the memory model __ATOMIC_RELEASE generates a data memory barrier with the option ish whereas I think that the one which has the "release" semantic is ishst (store before store). The attached patch implements my proposal. Thanks, Yvan -- gcc/